Hybrid Multicore Technology

Hybrid multifunction component system with component interface encapsulation including OS packet translator

for communication over unified data bus architecture:

A multiple generic microprocessor architectures with a set of two or more cores and groups of sub-processing components

and controlling components. Under this arrangement, different technology cores and functional components are organized

in a way that different technologies can collaborate as a single processor.

Unified Data Bus

The technology relates to multi-core integration, specifically for a multi-processing domain architecture.

Under the architecture, the first processing domain and the second processing domain can each comprise elements selected

from a group consisting of memory, I/O, cache, heterogeneous data buses, and processors.

3D Packaging

Self-organizing network with chip package having multiple interconnection configurations.

The technology relates to networks and chip packages specifically a self-organizing network with a 3D chip package

having back-end side interconnects and through silicon vias (TSVs). TSV technology is crucial for creating 3D packages

and 3D integrated circuits.

Memory and Process Sharing via Multiple Chipsets

A multiple chipset circuit design providing memory and process sharing via input/output (I/O) with virtualization.

The configuration reduces memory leakage and enhances overall performance and efficiency of the system.

Active Cache & Memory Virtualization on CPU and Memory Devices

This technology portfolio enables flexible and maximum utilization of cache memory and main memory system

that allows reconfigurable, dynamic cache, and works varies operation based on application demand from external/hybridized cores. 

Low-Power Consumption for Mobile Devices

This technology portfolio improves the power consumption of AI chips on the mobile devices.

Reliability & Monitoring IN-Circuit Technology

This technology portfolio enables semiconductor degradation monitoring and modeling using a sensor within functional circuit blocks

and at critical locations.